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19-1029; Rev 0; 10/07
Complete Single-Conversion Television Tuner
General Description
The MAX3541 complete single-conversion television tuner is designed for use in analog/digital terrestrial applications and digital set-top boxes. This television tuner draws only 760mW of power from a +3.3V supply voltage. The MAX3541 is designed to convert PAL or DVB-C signals in the 47MHz to 68MHz, 174MHz to 230MHz, and 470MHz to 862MHz bands to an intermediate frequency (IF) of 36MHz. The MAX3541 includes a variable-gain low-noise amplifier (LNA), multiband tracking filters, a harmonic-rejection mixer, a low-noise IF amplifier, an IF power detector, and a variable-gain IF amplifier. The MAX3541 also includes fully monolithic VCOs and tank circuits, as well as a complete frequency synthesizer. This highly integrated design allows for low-power tuner-on-board applications without the cost and power dissipation issues of dualconversion tuner solutions. The MAX3541 is specified for operation in the -40C to +85C temperature range and is available in a leadless 48-pin flip-chip (fcLGA) package.
Features
Low Power Consumption: 760mW (typ) from a +3.3V Supply Voltage Integrated Tracking Filters Low Noise Figure: 4.9dB (typ) Small 7mm x 7mm fcLGA Leadless Package IF Overload Detector Controls RF Variable-Gain Amplifier 2-Wire, I2C-Compatible Serial Control Interface
MAX3541
Ordering Information
PART TEMP RANGE PINPACKAGE PKG CODE L4877F-A
MAX3541ELM#G42 -40C to +85C 48 fcLGA-EP*
Applications
Televisions Analog/Digital Terrestrial Receivers Digital Set-Top Boxes
*EP = Exposed paddle. #Indicates RoHS-compliant and exempt from lead-free requirements.
Pin Configuration/Functional Diagram
ADDR2 ADDR1 XTALN XTALP GND_TUNE VTUNE MUX VCC LDO 38 VCC 48 47 46 45 44 43 42 41 40 39 37 VCC CP
SCL 1 /R SDA 2 VCC 3 UHF_IN 4 VHF_IN 5 RFGND2 6 LEXT 7 RFGND3 8 RFAGC 9 VCC 10 GND 11 GND 12 EP + SERIAL INTERFACE /N PD CP
36 IFOUT135 IFOUT1+ 34 IFOVLD VCO DIVIDER VREF 33 VCC 32 VCC 31 GND 30 IFIN+ 29 IFIN28 VCC 27 GND 26 IFAGC 25 IFOUT2+
MAX3541
13 GND
14 GND
15 GND
16 GND
17 GND
18 GND
19 GND
20 GND
21 GND
22 GND
23 VCC
24 IFOUT2-
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Complete Single-Conversion Television Tuner MAX3541
ABSOLUTE MAXIMUM RATINGS
VCC to GND ..............................................................-0.3V, +3.6V RFIN, IFIN_ IFOUT1_, IFOUT2_, IFAGC, RFAGC, VTUNE, LDO, MUX, CP, XTAL to GND ....................................-0.3V to (VCC + 0.3V) SDA, SCL, ADDR2, ADDR1 to GND......................-0.3V to +3.6V IFOUT__ Short-Circuit Duration .....................................Indefinite RF Input Power ...............................................................+10dBm Continuous Power Dissipation (TA = +70C) 48-Pin fcLGA (derate 25mW/C above +70C) ..............1.4W Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +165C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION! ESD SENSITIVE DEVICE
DC ELECTRICAL CHARACTERISTICS
(MAX3541 EV kit, VCC = +3.1V to +3.5V, TA = -40C to +85C, no RF signals at RF inputs, default register settings, VRFAGC = VIFAGC = +3V (minimum attenuation), unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.)
PARAMETER SUPPLY VOLTAGE AND CURRENT Supply Voltage Supply Current RF and IF AGC Input Bias Current RF and IF AGC Control Voltage (Note 1) Digital Input Logic-Level Low Digital Input Logic-Level High SERIAL INTERFACE Input Logic-Level Low Input Logic-Level High Input Hysteresis SDA, SCL Input Current Output Logic-Level Low Output Logic-Level High 3mA sink current VCC - 0.5 -10 0.7 x VCC 0.05 x VCC +10 0.4 0.3 x VCC V V V A V V 0.7 x VCC Receive mode (SHDN = 3V) Shutdown mode (SHDN = 0V) At +0.5V and +3V Minimum attenuation Maximum attenuation -50 +3 +0.5 0.3 x VCC +3.1 230 5 +50 +3.5 275 V mA A V V V CONDITIONS MIN TYP MAX UNITS
2
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Complete Single-Conversion Television Tuner
AC ELECTRICAL CHARACTERISTICS
(MAX3541 EV kit, VCC = +3.1V to +3.5V, TA = -40C to +85C, 75 system impedance, default register settings, VRFAGC = VIFAGC = +3V (minimum attenuation), unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.)
PARAMETER RF INPUT TO IFOUT1 OUTPUT 47 Operating Frequency Range (see Table 7) Output Frequency Gain specification met across these frequency bands Analog channel PIX carrier Digital channel center frequency Source impedance = 75, load impedance = 200 Selected channel Maximum gain (VRFAGC = 3V) Maximum gain (VRFAGC = 3V) At 12.5dB of gain Maximum gain (VRFAGC = 3V) At 12.5dB of gain Maximum gain (VRFAGC = 3V) At 12.5dB of gain 0dBmV PIX carrier level VHF input, 140MHz to 500MHz Beats, Converted to Output Gain Flatness Isolation Port-to-Port Isolation Image Rejection Spurious Leakage at RF Input VHF input, 500MHz to 1400MHz UHF input, 950MHz to 1400MHz 47MHz to 54MHz 5MHz to 50MHz, RF input to IF output, relative to desired channel Isolation between RF input ports at 215MHz Measured at 77.8MHz above desired channel's center frequency 5Hz to 65MHz 65MHz to 878MHz 1kHz Phase Noise (Single-Sideband) 10kHz offset 100kHz offset (1.5kHz loop bandwidth) 1MHz offset (1.5kHz loop bandwidth) Output Return Loss IF VARIABLE-GAIN AMPLIFIER Input Impedance Output Impedance Balanced Balanced (Note 1) 2000 300 Balanced 50 load 57 60 27 70 -40 -40 -80 -85 -105 -125 20 dB dBc/Hz 10 -38 -5 -40 -60 -50 -60 2.5 dBP-P dBc dB dBc dBmV dBc Maximum gain (VRAVGC = 3V) Minimum gain (VRAVGC = 0.5V) 33 174 470 38.9 36 41 -10 10 4.9 20 30 -10 dB dB dBm dBm dBm dBc 49 dB 68 230 862 MHz MHz CONDITIONS MIN TYP MAX UNITS
MAX3541
Voltage Gain
Input Return Loss Noise Figure Input IP2 (In-Band and Out-of-Band Tones) Input IP3 (In-Band and Out-of-Band Tones) Input P1dB Beats Within Output
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Complete Single-Conversion Television Tuner MAX3541
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX3541 EV kit, VCC = +3.1V to +3.5V, TA = -40C to +85C, 75 system impedance, default register settings, VRFAGC = VIFAGC = +3V (minimum attenuation), unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.)
PARAMETER CONDITIONS Source load = 1.1k, output load = 1k Maximum gain setting (VIFAGC = 3V) Minimum gain setting (VIFAGC = 0.5V) MIN 54 TYP 59 MAX 63 dB 21 1.2 2.5 27 7.3 < 0.35 VOUT = 1VP-P, 40dB < gain < 60dB (Note 1) -56 0.7 OD REG = 3 Negative polarity, overload reduces VDET (open collector, 0.3mA sink) 0.5 70 1 3.0 dB VP-P dB/V nV/Hz dB/dB dBc VP-P dB V V/V UNITS
Passband Voltage Gain
Passband Gain Flatness Output Voltage AGC Gain Slope Equivalent Input Voltage Noise Density Noise Figure Change vs. Attenuation IM3 Output Overload Attack Point Attack Point Accuracy Detector Output Voltage Range Detector Gain FREQUENCY SYNTHESIZER REFERENCE OSCILLATOR Frequency DIVIDERS RF N-Divider Ratio RF R-Divider Ratio LO PHASE DETECTOR AND CHARGE PUMP Comparison Frequency
32MHz to 40MHz (Note 1) VIFAGC = 3V (Note 1) VIFAGC = 3V to 0.5V (Note 1) At 36MHz, maximum gain (VIFAGC = 3V) (Note 1)
IF OVERLOAD DETECTOR (See the IF Overload Detector Section)
8 256 16 63 CP = 00 0.5 1 1.5 2 5 0.4 5 Tank frequency Tank oscillator gain 2200 4400 500 400 VCC 0.4 CP = 01 CP = 10 CP = 11 32,767 127 250
MHz
kHz
Charge-Pump Current
mA
Charge-Pump Three-State Current Charge-Pump Compliance Range Charge-Pump Current Matching LOCAL OSCILLATOR VCO Tuning Range VCO Tuning Gain 2-WIRE SERIAL INTERFACE Clock Frequency
nA V % MHz MHz/V kHz
Note 1: Guaranteed by design and characterization. 4 _______________________________________________________________________________________
Complete Single-Conversion Television Tuner
Typical Operating Characteristics
(MAX3541EV kit, VCC = +3.3V, VIFAGC = 3.0V, VRFAGC = 3.0V, TA = +25C, unless otherwise noted.)
MAX3541
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX3541 toc01
VHF VOLTAGE GAIN vs. RFAGC VOLTAGE
MAX3541 toc02
UHF VOLTAGE GAIN vs. RFAGC VOLTAGE
fRF = 801MHz 40 -40C
MAX3541 toc03
208
60 fRF = 64.5MHz VHF VOLTAGE GAIN (dB) 40 -40C
60
SUPPLY CURRENT (mA)
204
+85C
UHF VOLTAGE GAIN (dB)
200
20
+25C
20
+25C
196 +25C 192 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) 3.5 -40C
0
+85C
0 +85C
-20 0.5 1.0 1.5 2.0 RFAGC VOLTAGE (V) 2.5 3.0
-20 0.5 1.0 1.5 2.0 RFAGC VOLTAGE (V) 2.5 3.0
VHF VOLTAGE GAIN vs. FREQUENCY
MAX3541 toc04
VHF VOLTAGE GAIN vs. FREQUENCY
MAX3541 toc05
UHF VOLTAGE GAIN vs. FREQUENCY
MAX3541 toc06
46 -40C VHF VOLTAGE GAIN (dB) 44
55
60 -40C UHF VOLTAGE GAIN (dB) 50
VHF VOLTAGE GAIN (dB)
50
-40C
42
45
40
40
+25C +85C
40 +25C
30
+25C +85C
+85C 38 45 50 55 60 FREQUENCY (MHz) 65 70 35 170 180 190 200 210 FREQUENCY (MHz) 220 230
20 470 570 670 770 FREQUENCY (MHz) 870
VHF NOISE FIGURE vs. FREQUENCY
+55C +25C NOISE FIGURE (dB) 5 +85C
MAX3541 toc07
VHF NOISE FIGURE vs. FREQUENCY
MAX3541 toc08
7
7
+25C NOISE FIGURE (dB) 5
+55C
+85C
3
0C
-40C
3 0C -40C
1 48 51 54 57 FREQUENCY (MHz) 60 63
1 175 185 195 205 FREQUENCY (MHz) 215 225
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Complete Single-Conversion Television Tuner MAX3541
Typical Operating Characteristics (continued)
(MAX3541EV kit, VCC = +3.3V, VIFAGC = 3.0V, VRFAGC = 3.0V, TA = +25C, unless otherwise noted.)
UHF NOISE FIGURE vs. FREQUENCY
+85C +55C NOISE FIGURE (dB) 5
MAX3541 toc09
VHF NOISE FIGURE vs. RFAGC VOLTAGE
fRF = 224.25MHz +85C 16 NOISE FIGURE (dB) +55C 12 +25C 8
MAX3541 toc10
7
20
3 +25C 0C -40C
4
0C -40C
1 470 560 650 740 FREQUENCY (MHz) 830
0 1.8 2.0 2.2 2.4 2.6 RFAGC VOLTAGE (V) 2.8 3.0
UHF NOISE FIGURE vs. RFAGC VOLTAGE
MAX3541 toc11
VHF IMAGE REJECTION vs. FREQUENCY
-40C VHF IMAGE REJECTION (dB) 78 0C
MAX3541 toc12
20 +25C 16 NOISE FIGURE (dB) fRF = 631.25MHz
80
12
+55C
+85C
76 +25C +55C 72 +85C
8 -40C 0C 4
74
0 1.8 2.0 2.2 2.4 2.6 RFAGC VOLTAGE (V) 2.8 3.0
70 47 51 55 59 FREQUENCY (MHz) 63
VHF IMAGE REJECTION vs. FREQUENCY
MAX3541 toc13
UHF IMAGE REJECTION vs. FREQUENCY
MAX3541 to14
77 -40C 0C VHF IMAGE REJECTION (dB) 76
76 74 UHF IMAGE REJECTION (dB) 72 70 68 66 +85C -40C +55C 0C +25C
75 +25C 74
73 +55C 175 185 +85C
72
64 195 205 FREQUENCY (MHz) 215 225 470 570 670 770 FREQUENCY (MHz) 870
6
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Complete Single-Conversion Television Tuner
Typical Operating Characteristics (continued)
(MAX3541EV kit, VCC = +3.3V, VIFAGC = 3.0V, VRFAGC = 3.0V, TA = +25C, unless otherwise noted.)
VHF-L PHASE NOISE AT 10kHz OFFSET vs. CHANNEL FREQUENCY
MAX3541 toc15
MAX3541
VHF-L PHASE NOISE AT 10kHz OFFSET vs. CHANNEL FREQUENCY
MAX3541 toc16
-95
-90
VHF-L PHASE NOISE (dBc/Hz)
-99
VHF-L PHASE NOISE (dBc/Hz)
-97
-92
-94
-101
-96
-103
-98
-105 45 50 55 60 65 CHANNEL FREQUENCY (MHz) 70
-100 170 180 190 200 210 220 230 CHANNEL FREQUENCY (MHz) 240
UHF PHASE NOISE AT 10kHz OFFSET vs. CHANNEL FREQUENCY
MAX3541 toc17
VHF PHASE NOISE vs. OFFSET FREQUENCY
fRF = 64.5MHz VHF PHASE NOISE (dBc/Hz) -80
MAX3541 toc18
-80
-60
UHF PHASE NOISE (dBc/Hz)
-83
-86
-100
-89
-92
-120
-95 400 500 600 700 800 CHANNEL FREQUENCY (MHz) 900
-140 0.1 1 10 100 OFFSET FREQUENCY (kHz) 1000
UHF PHASE NOISE vs. OFFSET FREQUENCY
MAX3541 toc19
IFOUT1 NORMALIZED FREQUENCY RESPONSE (5MHz to 200MHz)
MAX3541 toc20
-60 fRF = 801MHz -70 UHF PHASE NOISE (dBc/Hz) -80 -90 -100 -110 -120 -130 0.1 1 10 100 OFFSET FREQUENCY (kHz)
5
0 IFOUT1 POWER (dBm)
-5
-10
-15
-20 1000 1 10 100 FREQUENCY (MHz) 1000
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Complete Single-Conversion Television Tuner MAX3541
Typical Operating Characteristics (continued)
(MAX3541EV kit, VCC = +3.3V, VIFAGC = 3.0V, VRFAGC = 3.0V, TA = +25C, unless otherwise noted.)
IFVGA VOLTAGE GAIN vs. IFAGC VOLTAGE
-40C 50 IFVGA VOLTAGE GAIN (dB) +25C 40 +85C 30
MAX3541 toc21
IFVGA IM3 vs. IFAGC VOLTAGE
-20
MAX3541 toc22
60
-20
VOUT = 1.5 VP-P -30 IFVGA IM3 (dBc) PIN -40 -40 -60 -50 IM3
20
10 0.5 1.0 1.5 2.0 IFAGC VOLTAGE (V) 2.5 3.0
-60 0.5 1.0 1.5 2.0 IFAGC VOLTAGE (V) 2.5 3.0
-80
Pin Description
PIN 1 2 3, 10, 23, 28, 32, 33, 37, 41, 44 4 5 6 7 8 9 11-22, 27, 31 24 25 26 29 30 34 35 36 38 NAME SCL SDA VCC UHF_IN VHF_IN RFGND2 LEXT RFGND3 RFAGC GND IFOUT2IFOUT2+ IFAGC IFINIFIN+ IFOVLD IFOUT1+ IFOUT1LDO DESCRIPTION 2-Wire Serial-Clock Interface. Requires a pullup resistor to VCC. 2-Wire Serial-Data Interface. Requires a pullup resistor to VCC. Power Supply Connections. Bypass each supply pin to ground with a 1000pF capacitor. UHF RF Input. Requires a DC-blocking capacitor. VHF RF Input. Requires a DC-blocking capacitor. RF Ground. Bypass to the PCB's ground plane with a 1000pF capacitor. Do not connect RFGND2 and RFGND3 together. RF VGA Supply Voltage. Connect through a 270nH pullup inductor to VCC. RF Ground. Bypass to the PCB's ground plane with a 1000pF capacitor. Do not connect RFGND2 and RFGND3 together. RF VGA Gain Control Voltage. Accepts a DC voltage from 0.5V (minimum gain) to 3V (maximum gain). Ground. Connect to the PCB's ground plane. Inverting IF VGA Output. Connect to the input of an anti-aliasing filter. Requires a DC-blocking capacitor. Noninverting IF VGA Output. Connect to the input of an anti-aliasing filter. Requires a DC-blocking capacitor. IF VGA Gain Control Voltage. Accepts a DC voltage from 0.5V (minimum gain) to 3V (maximum gain). Inverting IF VGA Input. Connect to the output of an IF-SAW filter. Noninverting IF VGA Input. Connect to the output of an IF-SAW filter. IF Overload Detector Open-Collector Output. Requires a 10k pullup resistor to VCC. Noninverting IF LNA Output. Requires a DC-blocking capacitor. Inverting IF LNA Output. Requires a DC-blocking capacitor. VCO LDO Bypass. Bypass to ground with a 0.47F capacitor.
8
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INPUT POWER (dBm)
Complete Single-Conversion Television Tuner
Pin Description (continued)
PIN 39 40 42 43 45 46 47 48 EP NAME GND_TUNE VTUNE MUX CP XTALN XTALP ADDR1 ADDR2 GND DESCRIPTION VTUNE Ground Connection. Connect to the PCB ground plane. All loop filter component GNDs must be connected to this pin (see the Typical Application Circuit). VCO Tuning Input. Connect to the PLL loop filter output. Test Output. Leave this pin unconnected during normal operation. Charge-Pump Output. Connect to PLL loop filter input. Crystal Oscillator Feedback. See the Typical Application Circuit. Crystal Oscillator Feedback. See the Typical Application Circuit. 2-Wire Serial-Interface Address Line 1. This pin along with ADDR2 sets the device address for the I2C-compatible serial interface. 2-Wire Serial-Interface Address Line 2. This pin along with ADDR1 sets the device address for the I2C-compatible serial interface. Exposed Paddle. Solder evenly to the PCB ground plane for proper operation.
MAX3541
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Complete Single-Conversion Television Tuner MAX3541
Detailed Description
Register Descriptions
The MAX3541 includes 11 programmable registers and 2 read-only registers. The 11 programmable registers include two N-divider registers, an R-divider register, a VCO register, an IFOVLD/Charge Pump/Filter Select register, a Control register, a Shutdown register, and Tracking Filter Control registers. These 11 programmable registers are also readable. The read-only registers include a status register and a ROM table data register. Recommended default bit settings are provided for user convenience only and are not guaranteed. The user must write all registers after power-up and no earlier than 100s after power-up.
Table 1. Register Configuration
MSB REGISTER NAME N-DIV High N-DIV Low R-DIV VCO IFOVLD, Charge Pump, and Filter Select Control Shutdown Tracking Filter Series Capacitor Tracking Filter Parallel Capacitor Tracking Filter ROM Address Reserved ROM Table Data Readback Status READ/ REGISTER WRITE ADDRESS D7 Both Both Both Both Both 0x00 0x01 0x02 0x03 0x04 0 N7 0 VCO4 0 D6 N14 N6 R6 VCO3 IFOVLD2 D5 N13 N5 R5 VCO2 IFOVLD1 DATA BYTE D4 N12 N4 R4 VCO1 IFOVLD0 D3 N11 N3 R3 VCO0 CP1 SHDN _RF SHDN _SYN TFS3 TFP3 TFA3 X TFR3 X D2 N10 N2 R2 LD CP0 SHDN _IFVGA 0 TFS2 TFP2 TFA2 X TFR2 X D1 N9 N1 R1 VDIV1 TF D0 N8 N0 R0 VDIV0 0 LSB
Both Both Both Both Both Both Read Read
0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C
0 SHDN _MIX1 TFS7 FLD 0 X TFR7 POR
0 SHDN _MIX0 TFS6 0 0 X TFR6 LD2
0 SHDN _IF TFS5 TFP5 0 X TFR5 LD1
0 SHDN _OD TFS4 TFP4 0 X TFR4 LD0
INPT1 0 TFS1 TFP1 TFA1 X TFR1 X
INPT0 0 TFS0 TFP0 TFA0 X TFR0 X
Table 2. N-DIV High Register (Address: 0000b)
BIT NAME RESERVED N[14:8] BIT LOCATION (0 = LSB) 7 6-0 RECOMMENDED DEFAULT 0 0000001 Must be set to 0. Sets the most significant bits of the PLL integer divider (N). Default integer divider value is N = 4688. N can range from 256 to 32,767. FUNCTION
10
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Complete Single-Conversion Television Tuner MAX3541
Table 3. N-DIV Low Register (Address: 0001b)
BIT NAME N[7:0] BIT LOCATION (0 = LSB) 7-0 RECOMMENDED DEFAULT 10101011 FUNCTION Sets the least significant bits of the PLL integer divider (N). Default integer divider value is N = 4688. N can range from 256 to 32,767.
Table 4. R-DIV Register (Address: 0010b)
BIT NAME RESERVED R[6:0] BIT LOCATION (0 = LSB) 7 6-0 RECOMMENDED DEFAULT 0 0010000 Must be set to 0. Sets the PLL reference divider (R). Default reference divider value is R = 64. R can range from 16 to 127. FUNCTION
Table 5. VCO Register (Address: 0011b)
BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT FUNCTION VCO select. Selects one of three possible VCOs. 00 = VCOs shut down 01 = Selects VCO1 10 = Selects VCO2 11 = Selects VCO3 VCO sub-band select. Selects one of eight possible VCO sub-bands. 000 = Selects SB0 001 = Selects SB1 010 = Selects SB2 011 = Selects SB3 100 = Selects SB4 101 = Selects SB5 110 = Selects SB6 111 = Selects SB7 Lock detect enable. 0 = Disabled 1 = Enabled VCO divider ratio select. 00 = Sets VCO divider to 4 01 = Sets VCO divider to 8 10 = Sets VCO divider to 16 11 = Sets VCO divider to 32
VCO[4:3]
7-6
10
VCO[2:0]
5-3
111
LD
2
1
VDIV[1:0]
1-0
10
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Complete Single-Conversion Television Tuner MAX3541
Table 6. IFOVLD, Charge Pump, and Filter Select Register (Address: 0100b)
BIT NAME RESERVED IFOVLD[2:0] BIT LOCATION (0 = LSB) 7 6-4 RECOMMENDED DEFAULT 0 000 Must be set to 0. Write content of ROM register OD[2:0] to this location. Selects the typical charge-pump current. 00 = 0.5mA 01 = 1mA 10 = 1.5mA 11 = 2mA Selects the tracking filter band of operation. 0 = VHF 1 = UHF Must be set to 0. FUNCTION
CP[1:0]
3-2
00
TF RESERVED
1 0
0 0
Table 7. Control Register (Address: 0101b)
BIT NAME RESERVED SHDN_RF BIT LOCATION (0 = LSB) 7-4 3 RECOMMENDED DEFAULT 0000 0 Must be set to 0000. RF shutdown. 0 = RF circuitry enabled 1 = RF circuitry disabled IF VGA shutdown. 0 = IF VGA enabled 1 = IF VGA disabled Selects the RF input. 00 = Selects VHF_IN, LPF enabled 01 = Selects VHF_IN, LPF disabled 10 = Selects UHF_IN 11 = Factory use only FUNCTION
SHDN_IFVGA
2
0
INPT[1:0]
1-0
01
Table 8. Shutdown Register (Address: 0110b)
BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT Mixer shutdown. 00 = Mixer enabled 01,10 = Factory use only 11 = Mixer disabled IF shutdown. 0 = IF section enabled 1 = IF section disabled IFOVLD shutdown. 0 = Power detector enabled 1 = Power detector disabled Frequency synthesizer shutdown. 0 = Synthesizer enabled 1 = Synthesizer disabled Must be set to 000. FUNCTION
SHDN_MIX
7-6
00
SHDN_IF
5
0
SHDN_OD
4
0
SHDN_SYN RESERVED
3 2-0
0 000
12
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Complete Single-Conversion Television Tuner MAX3541
Table 9. Tracking Filter Series Capacitor Register (Address: 0111b)
BIT NAME TFS[7:0] BIT LOCATION (0 = LSB) 7-0 RECOMMENDED DEFAULT 00001111* FUNCTION Programs series capacitor values in the tracking filter.
*See the RF Tracking Filter section.
Table 10. Tracking Filter Parallel Capacitor Register (Address: 1000b)
BIT NAME FLD RESERVED TFP[5:0] BIT LOCATION (0 = LSB) 7 6 5-0 RECOMMENDED DEFAULT 0 0 001001* FUNCTION Filter load bit. A 0 to 1 transition of this bit forces the loading of the ROM Table Data Readback register. Must be set to 0. Programs parallel capacitor values in the tracking filter.
*See the RF Tracking Filter section.
Table 11. Tracking Filter ROM Address Register (Address: 1001b)
BIT NAME RESERVED TFA[3:0] BIT LOCATION (0 = LSB) 7-4 3-0 RECOMMENDED DEFAULT 0000 0000* Must be set to 0000. Address bits of the ROM register to be read. FUNCTION
*See the RF Tracking Filter section.
Table 12. Reserved Register (Address: 1010b)
BIT NAME RESERVED BIT LOCATION (0 = LSB) 7-0 RECOMMENDED DEFAULT N/A FUNCTION Reserved. Do not program these bits during normal operation.
Table 13. ROM Table Data Readback Register (Address: 1011b)
BIT NAME TFR[7:0] BIT LOCATION (0 = LSB) 7-0 RECOMMENDED DEFAULT 00000000* FUNCTION Tracking filter data bits read from the device's ROM table.
*See the RF Tracking Filter section.
Table 14. Status Register (Address: 1100b)
BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT N/A FUNCTION Power-on reset. 0 = Status register has been read 1 = Power reset since last status register read VCO tuning voltage indicators. 000 = PLL not in lock, tune to the next lowest sub-band 001-110 = PLL in lock 111 = PLL not in lock, tune to the next higher sub-band Reserved.
POR
7
LD[2:0]
6-4
N/A
RESERVED
3-0
N/A
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Complete Single-Conversion Television Tuner MAX3541
2-Wire Serial Interface
The MAX3541 use a 2-wire I2C-compatible serial interface consisting of a serial-data line (SDA) and a serialclock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX3541 and the master at clock frequencies up to 400kHz. The master initiates a data transfer on the bus and generates the SCL signal to permit data transfer. The MAX3541 behaves as a slave device that transfers and receives data to and from the master. Pull SDA and SCL high with external pullup resistors (1k or greater) for proper bus operation. One bit is transferred during each SCL clock cycle. A minimum of nine clock cycles is required to transfer a byte in or out of the MAX3541 (8 data bits and an ACK/NACK). The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high and stable are considered control signals (see the START and STOP Conditions section). Both SDA and SCL remain high when the bus is not busy. To generate a not-acknowledge condition, the receiver allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse, and leaves SDA high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master must reattempt communication at a later time.
START and STOP Conditions The master initiates a transmission with a START condition (S), which is a high-to-low transition on SDA while SCL is high. The master terminates a transmission with a STOP condition (P), which is a low-to-high transition on SDA while SCL is high. Acknowledge and Not-Acknowledge Conditions Data transfers are framed with an acknowledge bit (ACK) or a not-acknowledge bit (NACK). Both the master and the MAX3541 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse.
Slave Address The MAX3541 has a 7-bit slave address that must be sent to the device following a START condition to initiate communication. The slave address is determined by the state of the ADDR2 and ADDR1 pins and is equal to 11000[ADDR2][ADDR1]. The eighth bit (R/W) following the 7-bit address determines whether a read or write operation occurs. Table 15 shows the possible address configurations. The MAX3541 continuously awaits a START condition followed by its slave address. When the device recognizes its slave address, it acknowledges by pulling the SDA line low for one clock period; it is ready to accept or send data depending on the R/W bit (Figure 1).
Table 15. MAX3541 Address Configurations
ADDR2 0 0 1 1 ADDR1 0 1 0 1 WRITE ADDRESS 0xC0 0xC2 0xC4 0xC6 READ ADDRESS 0xC1 0xC3 0xC5 0xC7
SLAVE ADDRESS
S
1
1
0
0
0
ADDR2
ADDR1
R/W
ACK
P
SDA
SCL
1
2
3
4
5
6
7
8
9
NOTE: TIMING PARAMETERS CONFORM WITH I2C BUS SPECIFICATIONS.
Figure 1. MAX3541 Slave Address Byte
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Complete Single-Conversion Television Tuner
Write Cycle When addressed with a write command, the MAX3541 allows the master to write to a single register or to multiple successive registers. A write cycle begins with the bus master issuing a START condition followed by the seven slave address bits and a write bit (R/W = 0). The MAX3541 issues an ACK if the slave address byte is successfully received. The bus master must then send to the slave the address of the first register it wishes to write to. If the slave acknowledges the address, the master can then write one byte to the register at the specified address. Data is written beginning with the most significant bit. The MAX3541 again issues an ACK if the data is successfully written to the register. The master can continue to write data to the successive internal registers with the MAX3541 acknowledging each successful transfer, or it can terminate transmission by issuing a STOP condition. The write cycle does not terminate until the master issues a STOP condition. Figure 2 illustrates an example in which registers 0 through 2 are written with 0x0E, 0xD8, and 0xE1, respectively. Read Cycle A read cycle begins with the bus master issuing a START condition followed by the seven slave address bits and a write bit (R/W = 0). The MAX3541 issues an ACK if the slave address byte is successfully received. The master then sends the 8-bit address of the first register that it wishes to read. The MAX3541 then issues another ACK. Next, the master must issue a START condition followed by the 7 slave address bits and a read bit (R/W = 1). The MAX3541 issues an ACK if it successfully recognizes its address and begins sending data from the specified register address starting with the most significant bit (MSB). Data is clocked out of the MAX3541 on the rising edge of SCL. On the 9th rising edge of SCL, the master can issue an ACK and continue reading successive registers or it can issue a NACK followed by a STOP condition to terminate transmission. The read cycle does not terminate until the master issues a STOP condition. Figure 3 illustrates an example in which registers 0 and 1 are read back.
MAX3541
START
WRITE DEVICE ADDRESS 11000[ADDR2][ADDR1]
R/W 0
ACK --
WRITE REGISTER ADDRESS 0x00
ACK --
WRITE DATA TO REGISTER 0x00 0x0E
ACK --
WRITE DATA TO REGISTER 0x01 0xD8
ACK --
WRITE DATA TO REGISTER 0x02 0xE1
ACK --
STOP
Figure 2. Example: Write Registers 0 Through 2 with 0x0E, 0xD8, and 0xE1, Respectively
START
WRITE DEVICE ADDRESS 110000[ADDR2][ADDR1]
R/W ACK 0 --
WRITE DEVICE WRITE 1ST REGISTER ACK R/W ACK ADDRESS ADDRESS START -- 110000[ADDR2][ADDR1] 1 -- 0x00
READ DATA ACK REG 0 D7-D0 --
READ DATA NACK REG 1 STOP -- D7-D0
Figure 3. Example: Read Data from Registers 0 and 1
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Complete Single-Conversion Television Tuner MAX3541
Application Information
RF Inputs
The MAX3541 features separate UHF and VHF inputs that are matched to 75. Both inputs require a DCblocking capacitor. The active inputs are selected by the input registers. In addition, the input registers enable or disable the lowpass filter, which can be used when the VHF input is selected. For the 47MHz to 68MHz, select the VHF_IN with the LPF filter enabled (INPT = 00). For 174MHz to 230MHz, select VHF_IN with LPF disabled (INPT = 01). For 470MHz to 862MHz, select UHF_IN (INPT = 10). loss for the desired received signal. The center frequency of each tracking filter is selected by a switched-capacitor array that is programmed by the TFS[7:0] bits in the Tracking Filter Series Capacitor register and the TFP[5:0] bits in the Tracking Filter Parallel Cap register. Optimal tracking filter settings for each channel varies from part to part due to process variations. To accommodate part-to-part variations, each part is factory calibrated by Maxim. During calibration, the y-intercept and slope for the series and parallel tracking capacitor arrays is calculated and written into an internal ROM table. The user must read the ROM table upon powerup and store the data in local memory (8 bytes total) to calculate the optimal TFS[7:0] and TFP[5:0] settings for each channel. Table 16 shows the address and bits for each ROM table entry. See the Interpolating Tracking Filter Coefficients section for more information on how to calculate the required values.
RF Gain Control
The gain of the RF low-noise amplifier can be adjusted over a typical range of 45dB with the RFAGC pin. The RFAGC input accepts a DC voltage from 0.5V to 3V, with 3V providing maximum gain. This pin can be controlled with the IF power-detector output to form a closed RF gain-control loop. See the Closed-Loop RF Gain Control section for more information.
RF Tracking Filter
The MAX3541 includes a programmable tracking filter for each band of operation to optimize rejection of out-of-band interference while minimizing insertion
Reading the ROM Table Each ROM table entry must be read using a two-step process. First, the address of the ROM bits to be read must be programmed into the TFA[3:0] bits in the Tracking Filter ROM Address register (Table 11).
Table 16. ROM Table
MSB DESCRIPTION ADDRESS D7 Reserved VHF Series Y-Intercept VHF Series Slope VHF Parallel Y-Intercept VHF Parallel Slope UHF Series Y-Intercept UHF Series Slope UHF Parallel Y-Intercept UHF Parallel Slope 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 OD2 VS0[7] VS1[7] VP0[7] VP1[7] US0[7] US1[7] UP0[7] UP1[7] D6 OD1 VS0[6] VS1[6] VP0[6] VP1[6] US0[6] US1[6] UP0[6] UP1[6] D5 OD0 VS0[5] VS1[5] VP0[5] VP1[5] US0[5] US1[5] UP0[5] UP1[5] DATA BYTE D4 X VS0[4] VS1[4] VP0[4] VP1[4] US0[4] US1[4] UP0[4] UP1[4] D3 X VS0[3] VS1[3] VP0[3] VP1[3] US0[3] US1[3] UP0[3] UP1[3] D2 X VS0[2] VS1[2] VP0[2] VP1[2] US0[2] US1[2] UP0[2] UP1[2] D1 X VS0[1] VS1[1] VP0[1] VP1[1] US0[1] US1[1] UP0[1] UP1[1] D0 X VS0[0] VS1[0] VP0[0] VP1[0] US0[0] US1[0] UP0[0] UP1[0] LSB
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Complete Single-Conversion Television Tuner
Once the address has been programmed, the data stored in that address is transferred to the TFR[7:0] bits in the ROM Table Data Readback register (Table 13). The ROM data at the specified address can then be read from the TFR[7:0] bits and stored in the microprocessor's local memory.
Closed-Loop RF Gain Control
Closed-loop RF gain control can be implemented by connecting the IFOVLD output to the RFAGC input. Using a 10k pullup resistor on the IFOVLD pin as shown in the Typical Application Circuit results in a nominal control voltage range of 0.5V to 3V.
MAX3541
Interpolating Tracking Filter Coefficients The TFS[7:0] and TFP[5:0] bits must be reprogrammed for each channel frequency to optimize performance. The optimal settings for each channel can be calculated from the ROM table data using the equations below: VHF filter:
TFS = INT[10 256 TFP = INT[10 256
[ VP0 [ VS0 x5+( x5+( VS1 - 1) x 1.5 x 10 -2 x f RF ] 256 ] VP1 - 1) x10 -2 x f RF ] 256 ]
VCO and VCO Divider Selection
The MAX3541 frequency synthesizer includes three VCOs and eight VCO sub-bands to guarantee a 2200MHz to 4400MHz VCO frequency range. The frequency synthesizer also features an additional VCO frequency divider that must be programmed to either 4, 8, 16, or 32 by the VDIV[1:0] bits in the VCO register based on the channel being received. To ensure PLL lock, the proper VCO and VCO sub-band for the channel being received must be chosen by iteratively selecting a VCO and VCO sub-band, then reading the LD[2:0] bits to determine if the PLL is locked. Any reading from 001 to 110 indicates the PLL is locked. If LD[2:0] reads 000, the PLL is unlocked and the selected VCO is at the bottom of its tuning range; a lower VCO sub-band must be selected. If LD[2:0] reads 111, the PLL is unlocked and the selected VCO is at the top of its tuning range; a higher VCO sub-band must be selected. The VCO and VCO sub-band settings should be progressively increased or decreased until the LD[2:0] reading falls in the 001 to 110 range. Due to overlap between VCO sub-band frequencies, it is possible that multiple VCO settings can be used to tune to the same channel frequency. System performance at a given channel should be similar between the various possible VCO settings, so it is sufficient to select the first VCO and VCO sub-band that provides lock.
UHF filter: :
TFS = INT[10 256 TFP = INT[10 256
[ UP0 [ US0 x5+( x5+( US1 - 1) x 5 x 10 -3 x f RF ] 256 ] - 10 UP1 - 1) x 5 x 10 -3 x f RF ] 256 ]
where: fRF = operating frequency in megahertz. TFS = decimal value of the optimal TFS[7:0] setting (Table 9) for the given operating frequency. TFP = decimal value of the optimal TFP[5:0] setting (Table 10) for the given operating frequency. VS0, VS1, VP0, VP1, US0, US1, UP0, and UP1 = the decimal values of the ROM table coefficients (Table 16).
Layout Considerations
The MAX3541 EV kit can serve as a guide for PCB layout. Keep RF signal lines as short as possible to minimize losses and radiation. Use controlled impedance on all high-frequency traces. The exposed paddle must be soldered evenly to the board's ground plane for proper operation. Use abundant vias beneath the exposed paddle for maximum heat dissipation. Use abundant ground vias between RF traces to minimize undesired coupling. To minimize coupling between different sections of the IC, the ideal power-supply layout is a star configuration, which has a large decoupling capacitor at the central VCC node. The VCC traces branch out from this node, with each trace going to separate V CC pins of the MAX3541. Each VCC pin must have a bypass capacitor with a low impedance to ground at the frequency of interest. Do not share ground vias among multiple connections to the PCB ground plane.
17
IF Overload Detector
The MAX3541 includes a broadband IF overload detector, which provides an indication of the total power present at the RF input. The overload-detector output voltage is compared to a reference voltage, and the difference is amplified. This error signal drives an open-collector transistor whose collector is connected to the IFOVLD pin, causing the IFOVLD pin to sink current. The nominal fullscale current sunk by the IFOVLD pin is 300A. The IFOVLD pin requires a 10k pullup resistor to VCC. The IF overload detector is calibrated at the factory to attack at 0.7VP-P at the IFOUT1. Upon power-up, the baseband processor must read OD[2:0] from the ROM table and store it in the IFVOLD register.
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Complete Single-Conversion Television Tuner MAX3541
Typical Application Circuit
4.3k 820pF 2.2k ** VCC 22pF 1000pF 8MHz 1000pF 220pF ** VCC ADDRESS 1 ADDRESS 2 ADDR2 ADDR1 XTALN XTALP VTUNE MUX VCC VCC 2.7k SCLK SCL SDATA VCC SDA VCC 100 UHF_IN VHF_IN 1000pF VCC LEXT 270nH 1000pF 2.7k IFOVLD 0.1F VCC 1000pF RFGND3 RFAGC VCC GND GND RFGND2 1 /R 2 3 4 5 6 7 8 9 10 11 12 EP + SERIAL INTERFACE /N 34 VCO DIVIDER VREF 33 32 31 30 29 28 27 26 25 PD CP 35 IFOUT1+ 10k IFOVLD VCC VCC GND IFIN+ IFINVCC GND IFAGC IFOUT2+ 0.1F VCC VCC 1000pF 1000pF IFOVLD VCC IF-SAW FILTER 0.1F 36 IFOUT1VCC 2.7k CP 220pF GND_TUNE VCC 47F 1000pF 1000pF LDO VCC 680nH 1000pF ** VCC 0.033F ** 560pF
48
47
46
45
44
43
42
41
40
39
38
37
1000pF
MAX3541
1000pF 2.7k VIFAGC
1000pF
13 GND
14 GND
15 GND
16 GND
17 GND
18 GND
19 GND
20 GND
21 GND
22 GND
23 VCC
24 IFOUT2-
ANTI-ALIASING FILTER IFOUT+ IFOUT-
VCC
1000pF ** CONNECT TO COMMON GROUND POINT AT PIN 39
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Complete Single-Conversion Television Tuner
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
48L LGA.EPS
MAX3541
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Complete Single-Conversion Television Tuner MAX3541
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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